AVP Project Status | |||
Project File: | AVP.ise | Current State: | Programming File Generated |
Module Name: | SYSTEM_STUB |
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No Errors |
Target Device: | xc3s1500-4fg456 |
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716 Warnings |
Product Version: | ISE 9.1.03i |
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? 9 6 20:45:35 2007 |
AVP Partition Summary | |||
No partition information was found. |
Device Utilization Summary | ||||
Logic Utilization | Used | Available | Utilization | Note(s) |
Number of Slice Flip Flops | 504 | 26,624 | 1% | |
Number of 4 input LUTs | 1,036 | 26,624 | 3% | |
Logic Distribution | ||||
Number of occupied Slices | 697 | 13,312 | 5% | |
Number of Slices containing only related logic | 697 | 697 | 100% | |
Number of Slices containing unrelated logic | 0 | 697 | 0% | |
Total Number of 4 input LUTs | 1,197 | 26,624 | 4% | |
Number used as logic | 1,036 | |||
Number used as a route-thru | 42 | |||
Number used for Dual Port RAMs | 16 | |||
Number used for 32x1 RAMs | 52 | |||
Number used as Shift registers | 51 | |||
Number of bonded IOBs | 315 | 333 | 94% | |
IOB Flip Flops | 54 | |||
Number of Block RAMs | 9 | 32 | 28% | |
Number of MULT18X18s | 1 | 32 | 3% | |
Number of GCLKs | 3 | 8 | 37% | |
Number of DCMs | 2 | 4 | 50% | |
Total equivalent gate count for design | 630,981 | |||
Additional JTAG gate count for IOBs | 15,120 |
Performance Summary | |||
Final Timing Score: | 0 | Pinout Data: | Pinout Report |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report |
Timing Constraints: | All Constraints Met |
Detailed Reports | |||||
Report Name | Status | Generated | Errors | Warnings | Infos |
Synthesis Report | Current | ? 9 6 20:40:07 2007 | 0 | 267 Warnings | 50 Infos |
Translation Report | Current | ? 9 6 20:40:27 2007 | 0 | 99 Warnings | 2 Infos |
Map Report | Current | ? 9 6 20:40:57 2007 | 0 | 118 Warnings | 3 Infos |
Place and Route Report | Current | ? 9 6 20:42:21 2007 | 0 | 116 Warnings | 1 Info |
Static Timing Report | Current | ? 9 6 20:42:36 2007 | 0 | 0 | 2 Infos |
Bitgen Report | Current | ? 9 6 20:43:21 2007 | 0 | 116 Warnings | 0 |